1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a driving method thereof and, more particularly, to a semiconductor integrated circuit suitably applicable to a successive comparison A-D converter, and a driving method thereof.
2. Related Background Art
With present development of digital signal processing, the A-D converters for converting an analog signal to a digital signal are important technology and the A-D converters of various methods (hereinafter referred to as AD converters) have been developed heretofore. Particularly in high-speed applications, the mainstream converters are flash AD converters wherein there are comparison voltages corresponding to all levels of a quantization range and in the case of N-bit conversion, the converter has (2N-1) comparators for concurrent comparison and encoding. Since the number of comparators was large, such AD converters were not suitable for applications to portable remote terminals and the like requiring low power consumption. Therefore, the successive comparison AD converters, which are AD converters of low power consumption, have widely been and are used.
FIG. 1 is a block diagram to show an example of the successive comparison AD converter. An analog signal to be converted is applied to input terminal 50 to be input to a (+) input terminal of comparator 51. Connected to a (-) input terminal of the comparator 51 is an output of D-A converter 54 whose input bit is set by successive comparison register 53 and which generates a comparison analog voltage.
A control circuit 52 sets a value of the successive comparison control register 53, based on a result of the comparator 51, to control the output of the DA converter 54. In the successive comparison AD converter, the analog signal input is successively converted bit by bit from MSB (Most Significant Bit) into a digital code. Let us consider successive comparison of N bits. In response to a control signal from the control circuit 52, the successive comparison register sets 1 at the N-th bit, which is the MSB, and 0 to the other bits. This code is applied to the DA converter 54 to be converted into an analog comparison signal Vda. In this case, the analog comparison signal Vda is generated as a voltage equal to a half of the entire quantization range, which is compared with the analog input signal Vin applied to the input terminal 50. When Vin&gt;Vda, the output from the comparator 51 becomes "H" to be sent to the control circuit 52. Receiving "H", the control circuit 52 rewrites the data in the successive comparison register so as to set 1 to the lower bit (MSB-1) while maintaining 1 in the MSB, which is the bit having been compared so far, and then sends the result to the DA converter 54. In this case, the MSB bit is determined to be 1 and the next comparison operation is carried out with setting 1 in the (MSB-1) bit. When Vin&lt;Vda, the output of the comparator 51 is "L" and is sent to the control circuit 52. Receiving "L", the control circuit 52 rewrites the data in the successive comparison register so as to change the MSB, which is the bit having been compared so far, from 1 to 0 and set 1 in the lower bit (MSB-1), and sends the result to the DA converter 54. In this case, the MSB bit is determined to be 0, and then the next comparison operation is carried out with setting 1 in the (MSB-1) bit. This operation is repeated while performing the comparison and register setting in order from the upper bit to the lower bit, so that the data of the successive comparison register finally becomes a binary code resulting from the A-D conversion of the analog input signal Vin applied to the input terminal 50.
For configuring a successive comparison AD converter with many bits, however, the successive comparison AD converter shown in FIG. 1 was not suitable because the number of bits of the DA converter 54 for generating the analog comparison voltage needed to be the same as the number of bits of the AD converter, resulting in increasing the circuit scale and in turn increasing power consumption. The conversion accuracy of the AD converter of the successive conversion method was mainly dependent upon errors of the DA converter 54, and the increase in the number of bits degraded the accuracy of DA converter 54. As a result, the AD convertor came to lack monotonicity and make a coding error.